Accommodating workload diversity in chip multiprocessors

Firstly, we present an overview of both traditional energy saving techniques and new developments in architectural approaches to energy-efficient processing.Secondly, we propose a pico MIPS architecture that serves as an architectural template for energy-efficient synthesis.The pico MIPS is a variable architecture RISC microprocessor with an application-specific minimised instruction set.Each implementation will contain only the necessary datapath elements in order to maximise area efficiency. Patt, (ASPLOS 2010) MT on CMPs Jose Renau† Karin Strauss Luis Ceze Wei Liu Smruti Sarangi James Tuck Josep Torrellas; Energy-Efficient Thread-Level Speculation on a CMP S. Keckler, ``Exploring the Design Space of Future CMPs,'' in PACT '01: Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques, pp. Mitigating Amdahl's Law through EPI Throttling Murali Annavaram Ed Grochowski John Shen, ISCA 2005 An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget Canturk Isci, Alper Buyuktosunoglu, Chen-Yong Cher, Pradip Bose and Margaret Martonosi Energy-Performance Tradeoffs in Processor Architecture and Circuit Design: A Marginal Cost Analysis, Omid Azizi et al, ISCA 2010 (link) "Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems" Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, and Yale N. Chinya, Hong Jiang, Xinmin Tian, Milind Girkar, Nick Y.

The pico MIPS architecture is presented, inspired by the MIPS, as an example of a minimal and energy efficient processor.Due to the relationship between logic gate count and power consumption, energy efficiency is also maximised in theprocessor therefore the system is designed to perform a specific task in the most efficient processor-based form.CSE 249A -- The Changing Role of the Microprocessor Core Instructor: Dean Tullsen tullsen at cs dot ucsd dot edu office hours by appointment This is a paper reading course. If you are enrolled for 4 units, you are expected to also do a research-style project, to be turned in before Monday of finals week. Support for Parallelism (should be more here): Carbon: Architectural Support for Fine-Grained Parallelism on Chip Multiprocessors Sanjeev Kumar Christopher J. in 31st International Symposium on Computer Architecture, June 2004. Yamazaki) EXOCHI: architecture and programming environment for a heterogeneous multi-core multithreaded system Pdf Perry H.

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